17 lines
335 B
Systemverilog
17 lines
335 B
Systemverilog
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module dut(
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input clk,
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input rst_n,
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input cnt_en,
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input clear,
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output reg [7:0] cnt
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);
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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cnt <= #1ns 0;
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else if(clear == 1)
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cnt <= #1ns 0;
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else if(cnt_en== 1)
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cnt <= #1ns cnt+1;
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end
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endmodule
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