init 6

.gitignore

@@ -9,6 +9,7 @@ simv.daidir
 */novas.rc
 */novas.conf
 *.fsdb
+tags
 
 2_vcs_comp/tb_lib/
 2_vcs_comp/dut_lib/

6_debug_access/Makefile

@@ -0,0 +1,12 @@
+include ../common_make
+
+.PHONY: clean comp sim all
+
+clean:
+	- rm -rf csrc simv.daidir ucli.key *.log simv *.h
+comp:
+	$(VCC) -full64 -sverilog +v2k -v2k_generate -kdb -ntb_opts uvm-1.2 -timescale=1ns/1ps \
+	-debug_access+r -f filelist.f -top tb
+sim:
+	./simv -ucli -do test.tcl
+all: comp sim

6_debug_access/ReadMe.md

@@ -0,0 +1,11 @@
+# `debug_access`选项对代码的影响
+
+## 快速上手
+
+```bash
+make clean all
+```
+
+## 实验结果
+
+待补充...

6_debug_access/filelist.f

@@ -0,0 +1,2 @@
+./rtl/dut.sv
+./rtl/tb.sv

6_debug_access/rtl/dut.sv

@@ -0,0 +1,29 @@
+/**
+ * File              : dut.sv
+ * License           : MIT
+ * Author            : Feng Bohan <1953356163@qq.com>
+ * Date              : 2025-05-22 15:37:52
+ * Last Modified Date: 2025-05-22 16:41:45
+ * Last Modified By  : Feng Bohan <1953356163@qq.com>
+ * -----
+ * Copyright © 2025 Feng Bohan. All Rights Reserved.
+ */
+module counter(
+    input clk,
+    input rst_n,
+    input cnt_en,
+    input cnt_clr,
+    output reg [7:0] cnt
+);
+    always @(posedge clk or negedge rst_n) begin
+        if(!rst_n) begin
+            cnt <= 0;
+        end else begin
+            if(cnt_clr == 1) begin
+                cnt <= 0;
+            end else if(cnt_en)begin
+                cnt <= cnt +1;
+            end
+        end
+    end
+endmodule

6_debug_access/rtl/tb.sv

@@ -0,0 +1,58 @@
+/**
+ * File              : tb.sv
+ * License           : MIT
+ * Author            : Feng Bohan <1953356163@qq.com>
+ * Date              : 2025-05-22 16:42:11
+ * Last Modified Date: 2025-05-22 18:31:12
+ * Last Modified By  : Feng Bohan <1953356163@qq.com>
+ * -----
+ * Copyright © 2025 Feng Bohan. All Rights Reserved.
+ */
+`timescale 1ns/1ps
+module tb();
+    import uvm_pkg::*;
+    /*****************
+    *  clock block  *
+    *****************/
+    parameter T = 10;
+    reg clk=0;
+    always #(T/2) clk = ~clk;
+
+    /******************
+    *  instance dut  *
+    ******************/
+    reg                         rst_n                           ;
+    wire                        cnt_en                          ;
+    wire                        cnt_clr                         ;
+    wire [7:0]                  cnt                             ;
+    counter dut(
+        .clk                    (clk                            ), //input
+        .rst_n                  (rst_n                          ), //input
+        .cnt_en                 (cnt_en                         ), //input
+        .cnt_clr                (cnt_clr                        ), //input
+        .cnt                    (cnt[7:0]                       )  //output
+    );
+
+    /***************
+    *  testbench  *
+    ***************/
+    initial begin
+        rst_n = 0;
+        repeat(2) @(posedge clk);
+        rst_n = 1;
+        //$monitor("dut.cnt =  %d at the time %t.", cnt, $time);
+
+        repeat(10) @(posedge clk);
+        $display("force: dut.cnt = %d", dut.cnt);
+        force dut.cnt = 1;
+
+        repeat(10) @(posedge clk);
+        $display("uvm_hdl_force: dut.cnt = %d", dut.cnt);
+        uvm_hdl_force("tb.dut.cnt", 2);
+
+        repeat(10) @(posedge clk);
+        $display("ucli_force: dut.cnt = %d", dut.cnt);
+        $stop();
+    end
+
+endmodule

6_debug_access/test.tcl

@@ -0,0 +1,4 @@
+run
+force tb.dut.cnt 'd3
+run 10ns
+finish

common_make

@@ -0,0 +1,17 @@
+LSB_RELEASE = $(shell lsb_release -is)
+LSB_VERSION = $(shell lsb_release -rs)
+ifeq (${LSB_RELEASE}, Ubuntu)
+	ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
+    	CC = gcc-4.8
+		CPP = g++-4.8
+	else
+    	CC = gcc
+		CPP = g++
+	endif
+else
+    CC = gcc
+	CPP = g++
+endif
+VCC = vcs -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
+		-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
+