/**
 * File              : tb.sv
 * License           : MIT
 * Author            : Feng Bohan <1953356163@qq.com>
 * Date              : 2025-05-22 16:42:11
 * Last Modified Date: 2025-05-22 18:31:12
 * Last Modified By  : Feng Bohan <1953356163@qq.com>
 * -----
 * Copyright © 2025 Feng Bohan. All Rights Reserved.
 */
`timescale 1ns/1ps
module tb();
    import uvm_pkg::*;
    /*****************
    *  clock block  *
    *****************/
    parameter T = 10;
    reg clk=0;
    always #(T/2) clk = ~clk;

    /******************
    *  instance dut  *
    ******************/
    reg                         rst_n                           ;
    wire                        cnt_en                          ;
    wire                        cnt_clr                         ;
    wire [7:0]                  cnt                             ;
    counter dut(
        .clk                    (clk                            ), //input
        .rst_n                  (rst_n                          ), //input
        .cnt_en                 (cnt_en                         ), //input
        .cnt_clr                (cnt_clr                        ), //input
        .cnt                    (cnt[7:0]                       )  //output
    );

    /***************
    *  testbench  *
    ***************/
    initial begin
        rst_n = 0;
        repeat(2) @(posedge clk);
        rst_n = 1;
        //$monitor("dut.cnt =  %d at the time %t.", cnt, $time);

        repeat(10) @(posedge clk);
        $display("force: dut.cnt = %d", dut.cnt);
        force dut.cnt = 1;

        repeat(10) @(posedge clk);
        $display("uvm_hdl_force: dut.cnt = %d", dut.cnt);
        uvm_hdl_force("tb.dut.cnt", 2);

        repeat(10) @(posedge clk);
        $display("ucli_force: dut.cnt = %d", dut.cnt);
        $stop();
    end

endmodule