59 lines
1.8 KiB
Systemverilog
59 lines
1.8 KiB
Systemverilog
/**
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* File : tb.sv
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* License : MIT
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* Author : Feng Bohan <1953356163@qq.com>
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* Date : 2025-05-22 16:42:11
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* Last Modified Date: 2025-05-22 18:31:12
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* Last Modified By : Feng Bohan <1953356163@qq.com>
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* -----
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* Copyright © 2025 Feng Bohan. All Rights Reserved.
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*/
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`timescale 1ns/1ps
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module tb();
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import uvm_pkg::*;
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/*****************
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* clock block *
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*****************/
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parameter T = 10;
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reg clk=0;
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always #(T/2) clk = ~clk;
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/******************
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* instance dut *
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******************/
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reg rst_n ;
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wire cnt_en ;
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wire cnt_clr ;
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wire [7:0] cnt ;
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counter dut(
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.clk (clk ), //input
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.rst_n (rst_n ), //input
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.cnt_en (cnt_en ), //input
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.cnt_clr (cnt_clr ), //input
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.cnt (cnt[7:0] ) //output
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);
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/***************
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* testbench *
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***************/
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initial begin
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rst_n = 0;
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repeat(2) @(posedge clk);
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rst_n = 1;
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//$monitor("dut.cnt = %d at the time %t.", cnt, $time);
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repeat(10) @(posedge clk);
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$display("force: dut.cnt = %d", dut.cnt);
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force dut.cnt = 1;
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repeat(10) @(posedge clk);
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$display("uvm_hdl_force: dut.cnt = %d", dut.cnt);
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uvm_hdl_force("tb.dut.cnt", 2);
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repeat(10) @(posedge clk);
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$display("ucli_force: dut.cnt = %d", dut.cnt);
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$stop();
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end
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endmodule
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